Memory addressing – Segmentation in Hardware (THE CRITIC AND IMPORTANT STUFF)

Physical Page: The basic unit memory management that kernel treats. Each architecture defines its own size in asm/page.h. There is a struct page for each physical page on the system.

MMU: Today microprocessor’s hardware (compound of Segmentation and Paging units) that manages memory and performs virtual to physical address translation. it contains the system’s page table

Logical Address: address of real mode (In this mode is possible the os’s bootstrap but it is just mapping 1MB in “linear addresses”) and protected mode (In this mode is enforced HW I/O and memory protection, it allows to work with a 4GB address space of linear addresses), it is based in a segment architecture where x86 DOS developers were forced to divide their programs into segments (click here for a profound explanation why logical addresses were created). This kind of address is included in machine language instructions to specify the address of an operand for an instruction. This address is conformed by a segment selector(16 bits) + offset(32 bits)

Linear address: address also known as virtual address (Usually represented by an unsigned integer to range from 0x00000000 to 0xFFFFFFFF). Every time a segment selector is loaded in a segmentation register (cs, ds , ss and other extra that may refer to arbitrary data segments. Such registers live upon processor to retrieve segment selectors quickly), the corresponding segment descriptor (8 bytes object describing segment characteristics) is loaded from a memory descriptor table into a non programmable CPU register, so segmentation unit is in charge of performing a segment descriptor base address’s field + Logical address offset to get a Linear one from a Logical one (result will be stored in gdtr or ldtr register).

Physical address: Used to address memory cells in memory chips. They correspond to the electrical signals sent along the address pins of the microprocessor to the memory bus.


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